Viewpoint: Routing is key to implementing DFM within the design flow Phil Bishop, President and CEO, Pyxis Technology EDA DesignLine (08/01/2007 7:34 H EDT) As the Semiconductor industry continues to march down the road to ever smaller geometries, one has to question at what point the current design methodologies and paradigms will break. Or maybe, more to the point, when does the SoC designer really have to worry about design for manufacturing (DFM). Apparently that day is now upon us, as we are already witness to a subtle but important shift in the way designers are creating the transistor portions of their designs. Almost all 65nm designs now use uni-directional poly-silicon gates to mitigate manufacturing issues associated with lithography and ion implantation. In its simplest form, this is an example of the use of restricted design rules or RDRs. RDRs at this stage still are confined to chip layers that make up the transistor devices, since these layers have the smallest dimensions and are the most susceptible to lithography and manufacturability issues. This shift has happened with almost no fanfare because it has affected a relatively small number of designers who work on the custom layout of intellectual property (IP) blocks (e.g., standard cells, memories). System-on-chip (SoC) designers who are working at 65nm are integrating these IP blocks with only a limited degree of concern for DFM. But what about the routing layers of the design? For 65nm designs, the dimensions of the routing layers are somewhat larger and easier to manufacture than the transistor layers. However, there are still fundamental yield and performance issues that should be reviewed for large, high-performing designs. When we move to 45nm and below, the physical dimensions of the routing layers look very similar to the dimensions of the transistor devices at 65nm. Does this mean that SoC designers may soon be forced to route designs with only uni-directional routes on a given layer? And what about the printability of all of the vias used to interconnect the routing layers? Employing a set of restricted design rules in the routing levels will be much more problematic. Unlike IP blocks, where layout regularity and re-use is the key to predicting manufacturability, the routing layers are by definition different for every unique design. There is very little "regularity" in the routing levels compared to a standard cell or IP block layout and the interconnect topology is highly dependent upon the design content and physical placement of IP blocks. At 45nm and below, all layout engineers, not just custom IP block designers, will need to be concerned about DFM. The opportunity to move manufacturing data further up the design flow is critical to improving the yield and manufacturability of advanced nanometer designs. Greater integration between DFM analysis tools, cell placement technologies, timing optimization tools, global routing, and the detailed routing phases of the physical design will be necessary to insure that critical yield limiters are designed out of the SoC before it reaches manufacturing. The time for SoC designers to truly integrate DFM into their design flows is upon us and it is coming in the form of new software architectures that fuse DFM knowledge with world class routing technology. For process technologies that are at 65nm and below, large advanced designs are already attaining yield improvements as high as 10% by having DFM analysis and cost functions embedded directly into advanced routing architectures. These next generation routing architectures must have support for a number of advanced process technologies and they must provide an integration path for both the design and manufacturing domains to enhance yield, improve routability and decrease the turnaround time for design closure. Routing is required for every IC design and it is the real DFM challenge for manufacturing and yield improvement of complex SoC devices. Neither relaxed nor restrictive design rules will represent an easy to fix to critical manufacturing issues within the nanometer routing domain. The only way to make a lasting change in terms of recognizing and eliminating semiconductor manufacturing issues is to emphasize that the EDA design flow architecture and infrastructure must change to meet this industry challenge. Fundamentally, EDA providers must pull more of the manufacturing data up into the design flow. The IC routing architecture will be the section of the design flow where DFM will be implemented for SoC design. It is here that decisions can be made with process data to ensure that yield and manufacturability can be optimized. Phil Bishop recently joined Pyxis Technology as president and CEO. He can be reached at [email protected] http://tinyurl.com/yonos2 --

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