Statistical static timing analysis: A view from the future Mustafa Celik EE Times (07/27/2007 9:52 H EDT) Since DAC 2005, there has been extensive discussion about using Statistical Static Timing Analysis (SSTA) to verify current and future generations of designs manufactured at 90 nm or below. Given the combination of physical effects and complexity in the most advanced processes and designs, timing verification needs to account for intra-die and die-to-die variability in manufacturing. Adding to this, the influence of voltage and temperature margins has led to the exploding number of design "corners" to be analyzed by engineers. Timing closure is a real challenge, too, requiring dozens of analysis runs that each take many hours to complete. And in the end, there are still questions about whether pessimism could have been reduced or whether the yield would be acceptable. Compared with traditional timing tools, SSTA completes an analysis in one or two runs; reports all of the process, voltage and temperature effects on design timing; and displays the yield that can be expected. There are several advantages to this approach that can be immediately used by design teams. First, pessimism in the design can reduced. For example, the possible reduction of arrival times by 10"15 percent can cut power consumption. Second, dramatically faster analysis can lead to faster timing closure. Third, different scenarios and implementations can be more quickly explored to understand yield, performance and cost trade-offs. One integrated device manufacturer (IDM) has suggested that "intelligent" corner selection can be done instead of SSTA. Intelligent corner design is workable in the special case of microprocessor or custom design, in which a deep understanding of process and environmental conditions is available due to a long design cycle, large design teams and the use of "binning" for the manufactured parts. But for smaller ASIC teams dealing with different synthesized designs and a fixed performance target, the corners are design-dependent; and sometimes even path-dependent. Therefore, picking the right intelligent corners is not easy. For those design teams that do want to choose intelligent corners, SSTA would be the ideal tool. Although designers generally do not know how to deal with probability distributions, they are interested in determining how much pessimism exists, whether the design is robust and what optimization can be done for power or performance. So the question designers ask themselves is not "what will my yield be at a given frequency," but rather "given my target spec and my timing report, where can I make improvements?" SSTA is a tool that can deliver these answers. A phased approach is the easiest way for design teams to start working with statistical analysis. Statistically aware timing analysis can be used for analyzing corners in a traditional deterministic flow and for analyzing some of the random and systematic variations that affect design performance and yield. Because SSTA is engineered to run verification quickly, the analysis of multiple modes of circuit operation is practical, too. With all of its capabilities, SSTA is, in fact, a superset of the approaches described in the recent EE Times article "Re-thinking SSTA." Making full use of SSTA requires statistical library characterization and layout extraction. Statistical library creation is now possible and practical with new methods delivering breakthroughs in characterization speeds 10 times greater than those of traditional library tools. Combined with new standards for describing statistical information, CAD teams have a clear path ahead for the adoption of statistical characterization flows. Although systematic variations do not have to be modeled in SSTA, there are advantages to doing so. SSTA gives IDM design teams an additional way of understanding the performance trade-offs for their design, particularly as new processes are being developed. Because SSTA is a general solution that can display the analysis for both systematic and random variations, it can also determine how each kind of variation will affect the overall performance of the design. The consensus for leading-edge silicon nodes is that random or mismatch variations will very soon begin dominating designs, and this will require SSTA. By the 45-nm silicon node, design teams will need to adopt SSTA as a part of their design-for-manufacturability (DFM) infrastructure to control uncertainty in design. Design tool developers are working to create an architecture and platform that delivers all of SSTA's benefits, the execution speed and capacity to handle the expanded set of calculations and applicability to many different application areas such as wireless, graphics and low-power. From our point of view, we can clearly see the future of SSTA, and it is bright. —Mustafa Celik is CEO of Extreme DA, a privately-held electronic design automation company based in Palo Alto, Calif. http://tinyurl.com/2w3hqm --

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