Design-to-fab of 45-nm ICs is variability issue Sudhakar Jilla (07/26/2007 4:23 H EDT) At 65/45 nm and below, a new world order is beginning to emerge that challenges all our previous experience in IC design and manufacture. Absolute design rules and the traditional signoff process are no longer enough to achieve acceptable manufacturing yield and performance. Systematic defects due to process and environmental variations have overtaken random defects as the major causes of yield limitations at 65/45-nm geometries. Designers have always had to constrain a growing number of design elements in less space, but with systematic variation, many of those features are now subject to many more geometric influences, which complicates the task. Designers are also being asked to create designs that can accommodate and minimize the effects of manufacturing variabilities across dies, wafers, lots and even manufacturing locations. Today, solving or minimizing manufacturing and yield issues in the design cycle can save enormous amounts of money and time in the overall design-to-production process. The causes of variability are threefold: * Operational * Global * Local Operational variability Increasing operational complexity requires devices that can operate in multiple modes, each of which has differing (and sometimes conflicting) design constraints. For example, a cell phone chip might need to operate in a Sleep mode, requiring very little power drawdown, and a Standby mode, where power usage must be slightly increased in anticipation of a move to Active mode, where power needs are at their highest. The challenge in the design of these multiple mode ICs at 65/45 nm is to analyze and optimize the multiple-mode design constraints concurrently, while also accounting for global and local variations. In operational design variation, a single circuit implementation has to satisfy two operating frequencies (50 MHz and 250 MHz) with different sets of input/output delays under different operating conditions. Complex chips have several such operational modes, which results in the creation of multiple timing graphs. All of these need to be analyzed and optimized concurrently to ensure successful design closure. Global variations are those that occur across die, whether those die are on the same wafer, different wafers, different lots or even different fabs. While many of these factors are well documented, some surprising exceptions have been discovered in the nanometer world. For example, engineers have long known that such external factors as ambient temperature and supply voltage can change the electrical characteristics of chip devices. For the past 50 years, experience has always shown the worst-case scenario to be a combination of low voltage, slow process and high temperature. At the 65/45-nm mode, we are finding that it is low voltage, slow process and low temperature that create the worst timing issues. Designers have to rethink and remodel their designs, using simultaneous analysis across multiple corners, to account for these new forms of variations. Local variations Local design variations occur within any one chip. Device and interconnect geometry variability is one example of a common design issue that has taken on new significance with the move to smaller geometries. Photolithographic dependencies, device voltage variations and local metal thickness variation all become more challenging as design size decreases and design complexity increases. Traditional design flows are breaking down in the nanometer world. Because these flows were never designed to handle more than one or two variability conditions, attempting to incorporate multiple-mode, multiple-corner analysis results in extensive and iterative "analyze and fix" cycles, adding time and cost to the production schedule. In both global and local variability, traditional manufacturing variability issues-such as unevenness in film deposition or dielectric thickness variations caused by chemical-mechanical planarization (CMP)-become more critical at the 65/45-nm level. With ever-smaller margins for error, dishing or erosion can have drastic impacts on line resistance, coupling capacitance and other performance factors that reduce yield, performance and reliability. While manufacturing variation cannot be eliminated (yet!), designers are learning to mitigate the impact of these parametric variations by modeling multiple corners to determine how to optimize the design for yield. Due to the image variability caused by the lithographic limitations of 65/45-nm mask manufacture and the actual die fabrication process, the design shapes and geometries for both devices and interconnects must be intentionally distorted and carefully manipulated to create an actual 'as manufactured' product that achieves the desired performance specifications. Design verification tools must be able to predict and model the potential impact of these lithographic inaccuracies, so that designers can adjust the design parameters and geometries for the best possible manufacturing result, both globally and locally. Fabs are constantly experimenting with new combinations of materials and processes, attempting to develop new amalgamations that are better suited to the demands and restrictions of 65/45-nm production. Changes in material properties create a ripple effect back to the design process, as designers learn to adapt their designs to take advantage of new and changed performance and production capabilities. How can we adapt and thrive in the nanometer world? The answer is always the same: 'It depends.' Whatever tools and processes are used, they must help recognize, evaluate and optimize design choices. What's more, yield and performance will be accomplished only through the integration of design and manufacturing. Communication between manufacturing and design will help identify new anomalies that arise at smaller geometries, allowing for appropriate and timely modification of design rules, design models, test scenarios and manufacturing requirements. And because models and tests are only as good as the assumptions and results used to create them, ensuring their ongoing accuracy can only happen with repeated interactions between design and manufacturing. As it is apparent that the traditional implementation products now in the market cannot scale to meet the variability challenges of large high-performance designs at 65/45 nm and below, a new architecture is needed to enable us to comprehensively address variability in all its guises-variations in design contexts, variations due to device/interconnect scaling, and variations in manufacturing processes. A solution that can concurrently analyze and optimize such effects throughout the design flow will remove or minimize the unpredictability of design closure and empower designers to stay on schedule and meet their market windows. About the author Sudhakar Jilla is marketing director for Place & Route Products at Mentor Graphics. He holds a master's degree in electrical engineering from the University of Hawaii and an MBA from the Leavey School of Business, Santa Clara University. http://tinyurl.com/yu45ty --

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