Semicon panel: Design-for-manufacturability no longer a luxury Nicolas Mokhoff EE Times (07/23/2007 1:05 H EDT) SAN FRANCISCO — As the semiconductor industry tries to resolve design-for-manufacturability (DFM) issues, it can learn from the history of design-for-test, a panel of EDA gurus observed here at Semicon West. "True DFM is big question mark, and if it follows in the footsteps of DFT it will take seven years for true DFM to take roots within the design community," said panel moderator Gary Smith, president of Gary Smith EDA. Semiconductor companies essentially "forced" DFT on design engineers, and it took seven years for designers to accept it. Semiconductor makers now need to compel design and process engineers to use DFM tools and methodologies, Smith said. A new coalition formed by the Silicon Integration Initiative (Si2) now officially defines DFM as design-for-manufacturability rather than design-for-manufacturing. Lars Liebman, distinguished engineer at IBM and an activist in the Si2 standards effort, said the definition more accurately reflects the idea that "designs need to have the proper 'hooks' to be manufactured flawlessly." Smith believes to maximize device yields, it is necessary to understand the whole supply chain environment. "If you don't understand the entire semiconductor infrastructure, either you are not going to come up with marketable products or you're not going to be able to solve the problems," he said. Richard Tobias, president and CEO of Cake Technology, said that for a fabless semiconductor company, "in the past, it was a big worry if you were going to get DFM data from various foundries." The industry faced a lot of signal integrity issues at the 130-nanometer node, Tobias noted. "We really didn't understand what we needed to do so we could build chips that would yield well," he said. "At 90 nm and 65 nm, it is pretty well understood what the issues are, and the tool flows are fairly stable and usable. You can build products and be fairly certain they are going to be good products. DFM will have to grow into what the issues will be as we move to 45 nm and beyond." Nitin Deo, vice president of marketing and business development at Clear Shape Technologies, said the design side deals with a lot of variation, "which means that whatever you think you are designing isn't what you are getting in silicon, and in the extreme case you get failures and yield problems." Foundries, Deo said, need to tell designers how to make designs manufacturable: "Model-based analysis needs to be implemented instead of design rule checkers at 45 nm, and it needs to be certified by the fabs." DFM has gone through three eras so far, according to Joe Sawicki, vice president and general manager at Mentor Graphics. "In the 45- to 32- nm era, DFM is a must in order to feel confident about getting verified chips out on time." "DFM is a homogeneous solution for a heterogeneous environment," said IBM's Liebman. "One solution does not fit all designs." He suggested the industry think of DFM not as a node-specific phenomenon, but "one whose benefits are product-specific and schedule-specific." "It is an extraordinarily tough technical problem," Liebman said, "and it's not just about polygon pushing to get a layout right." It will take a tremendous amount of CPU cycles to calculate the data for design optimization for error -free manufacturing. Liebman pointed to a specific project at a research consortium among IBM, Rensellaer Institute and New York State that is working to solve "variation-aware circuit design" using the power of a world leading supercomputer shared by the consortium. "We need such collaboration across industry and academia, with serious investments in order to resolve what is becoming the problem of 'computational scaling' at the 45-nm and lower nodes," he said. In his keynote at Semicon West, Synopsys Inc. chairman Aart de Geus described how he believes such collaborations should unfold. "Scale complexity" and "system complexity" make life tougher as 45-nm designs come out the door, he said, but they "also provide opportunities for the EDA community." The Synopsys chairman proposed a "tweak" to the DFM flow. "We need to make the transistors 'stress' in order to optimize their implementation," de Geus said. "At 45 nm and below, this will accelerate designs to market." http://www.eetimes.com/news/design/showArticle.jhtml?articleID=201200505 --

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