Conference puts IC routing to the test Richard Goering EE Times (02/08/2007 1:07 H EST) SANTA CRUZ, Calif. — Aiming to spur advances in IC routing technology, the International Symposium on Physical Design (ISPD) will initiate a routing contest at this year's meeting, to be held March 18-21 in Austin, Texas. ISPD has also released the technical program for the symposium. ISPD is an annual symposium that draws from both industry and academia, and showcases new research in IC physical design. For the past several years, ISPD has run an IC placement contest. That contest, organizers say, has led to improvements in IC placement algorithms, and has resulted in a benchmark suite derived from industrial ASIC designs. Patrick Madden, associate professor of computer science at the State University of New York (Binghamton) and ISPD 2007 general chair, said that 14 teams have already signed up for the routing contest, with several more expected. "In the past two or three years, routing has gotten to be a hot topic, and there are a ton of startups in this area," Madden said. "In the hopes of nailing down what works and what doesn't, we'll be doing a global routing contest this year." Madden said the routing contest will involve relatively simple metrics, such as congestion, wire length, and vias. He said there will be a new set of routing benchmarks based on the placement benchmarks from last year. In future years, he said, organizers hope to add design for manufacturability (DFM) objectives. Meanwhile, the placement contest will continue, Madden said. Last year, he noted, there were 10 strong entries. "The progress in placement in the past couple of years has been off the charts," he said. "I'm willing to bet that another five percent or so has been shaved off the best results from last year." The technical program for ISPD 2007 is now available at the conference web site. It starts Monday, March 19, with a keynote address by Jim Khale of IBM on the physical design features and methodology of the IBM Cell architecture. Technical paper sessions include multicore and DFM, circuit analysis and optimization, future interconnects, placement, routing, statistical and physical DFM, and clock and interconnect. A Monday afternoon panel session discusses tradeoffs between "rules and tools" for IC manufacturablity, and the placement and routing contest awards will be given in a Tuesday session. IC process variability emerged as a major theme at the ISPD 2006 conference last year. http://www.eetimes.com/news/design/showArticle.jhtml?articleID=197004462 --

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