TSMC DFM format empowers fabless design TSMC this week will roll out a 65-nanometer design for manufacturability (DFM) "ecosystem" and a unified data format that will bring process model information to fabless semiconductor makers. The announcement may help close the gap between fabless designers and IDM designers, who can obtain process information from their own fabs. At a TSMC Technology Symposium in San Jose, Calif. Wednesday (May 17), the company will announce its 65-nm Compliant Design Support Ecosystem. Its centerpiece is the DFM Unified Format (DUF), which claims to provide all the information needed for lithography process checks, critical area analysis, and chemical mechanical polishing (CMP) analysis. It will be available for both 90- and 65-nm processes in July. To use the format, EDA tools must undergo a rigorous qualification that includes tests for accuracy, usability and run times. Vendors who have qualified tools include Anchor Semiconductor, Cadence Design Systems, Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, Predictions Software, and Synopsys. "This is an enormous step forward," said Ed Wan, senior director of design services marketing at TSMC. "We are dealing not just with tools, but with an entire ecosystem. We set into motion an initiative that will weave DFM into every component of our design alliance partner program." The initiative, he said, will serve TSMC's alliance programs with EDA vendors, library and intellectual property (IP) providers, and independent design centers. "We're moving DFM capability to the designer's desktop, rather than what's been announced in the past, which is primarily the ability to run DFM functions at the foundry site." This move by the leading pure-play foundry may overcome one of the biggest stumbling blocks in sub-90 nm design — the difficulty that fabless vendors have had in securing proprietary process data from foundries. The initiative supports the model-based DFM that's becoming essential at 65 nm and below, where mere reliance on design rules is no longer sufficient to ensure good yields. TSMC introduced a 65-nm reference flow in June 2005. At that time, the company also rolled out Yield Plus, a set of process-related toolkits, and Yield Pro, a set of design services. TSMC quietly launched a "DFM-Compliant Initiative" that now includes 18 third-party companies. Now, however, TSMC is bringing DFM capabilities more directly to customers through its DFM Unified Format and "ecosystem" of qualified tools. The DUF data is provided in what TSMC calls DFM Data Kits (DDKs). These are provided directly to customers, and the format is licensed to selected EDA vendors so that tools can be qualified. TSMC has also defined a library and IP compliance procedure that involves three proprietary tools — layout parasitic extraction (LPE), a layout enhancer, and lithography process check (LPC). Finally, TSMC has worked with its Design Center Alliance members to help them implement DFM for 65-nm designs. http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187202879 --

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