课程名称︰虚拟机器 课程性质︰选修 课程教师︰徐慰中 开课学院：电资学院 开课系所︰资工所、网媒所 考试日期（年月日）︰2015.04.09 考试时限（分钟）： 试题 : 1) Which of the following programs make intrinsically compatible extremely difficult? A) A program which uses OpenGL intensively B) A program does a checksum of all memory locations that it can reach. C) A guest process uses all virtual address space D) A program which is sensitive to FP accuracy based on 80 bit Intel extended precision format 2) To maintain trap compatibility, which of the following instructions (after being translated into target code) are more constrained to be removed A) Load instructions B) Store instructions C) FP instructions D) Integer instructions 3) What is the main reason that ordinary load instructions should not be used as cache prefetch instructions? A) They will modify target registers B) They may generate traps C) They will waste memory bandwidth D) They have long latency since they must wait until the target register is loaded. 4) When we said "runtime code" "runtime data" in this chapter, what does it mean by "runtime"? A) The VM software layer B) The EM manager, the interpreter, the DBT translator, and so on. C) The OS D) The guest process 5) With binary translation, when the emulation is changing from the runtime mode to the emulation mode, which of the following memory sections must change protections? A) Guest data B) Code Cache C) Runtime Code D) Runtime Data E) Guest Code 6) In process VM, which of the following memory areas are very difficult to protect against illegal accesses from the translated code. A) Guest code B) Runtime data C) Memory mapped architecture states D) Guest read only data 7) Why are interrupts easier to handle than traps in process VMs? A) Precise architecture states can be more easily recovered B) Interrupts can be delayed indefinitely C) Interrupts can be ignored D) Interrupts can be handled at a more convenient time 8) In a process VM, when an interrupt occurs, the runtime needs to unchain blocks for the currently executed block. Why? A) Unchaining is to avoid looping B) Unchaining is to force emulation goes back to the emulation engine C) Unchaining is to force the emulation manager to recover the precise guest states D) Unchaining is to remove stale code 9) For process VMs, to emulate OS calls under the same OS, what tasks must be done? A) A wrapper routine (jacket) for each system call B) A copy of the guest OS code must be provided C) Type conversions of passed parameters may be required D) Instruction to Instruction binary translation is required for each emulated system calls 10) Code caches are often managed with the simple flush-when-full policy. Why not use the allocate-when-needed policy? Which of the following are true or even partially true? A) Memory thrashing may be more expensive than re-translations B) Code cache management is needed anyway even if the allocate-when-needed policy is used C) Flush has the advantage of getting rid of stale translated traces D) Allocate-when-needed may end up with decreased locality 11) If intrinsic compatibility is required, which of the following instruction optimizations are not allowed: A) dead code elimination B) load reordering C) store reordering D) merging FADD and data dependent FMUL into one FMAC instruction 12) In terms of memory protection emulation, which of the following cases are easier to handle: A) Host page size is larger than the guest page size B) Guest offers variable size pages, host does not C) Guest page size is larger than the host page size D) Host offers variable size pages 13) To recover the guest PC at a trap could be as simple as recovering a PC at a debug trap, why some process VMs prefer to use a re-translation approach: A) Space overhead for side tables may be excessive B) Side tables are hard to maintain when optimizations are performed C) Frequency for traps with precise states is supposed to be low D) Less engineering efforts 14) A Process VM migrates ARM code to x86. If an application registered a data mis-alignment trap handler, how should the VM check for such mis-alignment traps? A) Let the host trap and catch it B) Using the interpreter to check for this trap C) Generate explicit instructions to check for such traps D) Ignore that trap, claim that we only support extrinsic compatibility 15) How is a code cache (as in process VM) different from a hardware cache? A) Code cache is managed by SW B) Code cache miss is more expensive than a HW cache miss C) Code cache lines are variable length D) Code cache lines have no tags Ans: 1) B, C, D 2) A, B, C 3) B 4) A, B 5) B, C, D 6) C 7) A, D 8) A, B, C 9) A, C 10) A, B, C, D 11) A, B, C, D 12) C, D 13) A, B, C, D 14) B, C 15) A, B, C, D --

※ 发信站: 批踢踢实业坊(ptt.cc), 来自: 114.24.41.217 ※ 文章网址: https://webptt.com/cn.aspx?n=bbs/NTU-Exam/M.1429950180.A.D6A.html ※ 编辑: rod24574575 (114.24.78.41), 06/13/2015 08:42:31