作者leviliang (levi)
看板Grad-ProbAsk
标题[理工] [计组]-台大资工101 CPU Performance
时间Mon Feb 4 11:10:00 2019
Part II第2题
[CPU Performance]
Calculate the performance of a processor taking into account stalls due to
data cache and instruction cache misses.
‧The data cache has a
92% hit rate and a
2-cycle hit latency. Assume that
latency to memory and the cache miss penalty together is
100 cycles.
‧The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles.
Assume the load never stalls a dependent instruction and assume the
processor must wait for stores to finish when they miss the cache.
Finally, assume that instruction cache misses and data cache misses never
occur at the same time.
(a) Calculate the average memory access latency for the data cache.
(b) Assume the
base CPI using a perfect memory system is
1.0. Calculate the
additional CPI of the pipeline due to the Instruction cache stalls.
(c) Same as (b), but calculate the additional CPI due to the data cache stalls.
(d) Assume 30% of instructions are loads and stores. Calculate the overall CPI
for the machine.
Ans:
(a) AMAT =
2 +
0.08 * 100 = 10
(b) The additional CPI due to instruction cache stalls = 1 * 0.1 * 50 = 5
(c) Suppose 30% of instructions are loads and stores.
The additional CPI due to data cache stalls = 0.3 * 0.08 * 100 = 2.4
(d) Overall CPI =
1 + 0.3 *
0.08 * 100 + 1 * 0.1 * 50 = 8.4
请教各位大大，为何(d)的Overall CPI不需要加上
2-cycle hit latency
有爬了之前的文但并没有看到相关的讨论，
想了很久也没想到合理的解释，
麻烦各位大大了！
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※ 编辑: leviliang (39.12.110.193), 02/04/2019 11:32:13
1F：推 Dora5566: 答案错吧 02/04 14:04
我後来继续算别题，
发现虽然很多都需要hit latency计算在内，
不过通常是因为分为L1与L2的hit latency，
所以Overall CPI的
base CPI才需要使用hit latency来计算。
但这题却是只有data与instruction cache，
且一开始仅提供data cache的
hit latency。
後来(b)已给定
base CPI=1，
这应是代表data cache与instruction cache的
total hit latency
如此解释，应该就合理了吧
2F：推 b10007034: 题目出得好奇怪... 02/04 17:56
同意b大...
※ 编辑: leviliang (39.12.110.193), 02/04/2019 18:24:47