作者chris750630 (何去何从？)
看板Grad-ProbAsk
标题Re: [理工] [计组]-快取失误率
时间Mon Jan 18 21:37:57 2010
※ 引述《gn00618777 (123)》之铭言：
: Suppose we have a processor with base CPI 1.0,assuming all reference hit
: in the primary cache, and a clock reate of 500MHZ. Assume a main memory
: access time of 200ns,including all the miss handing. Suposse the miss
: rate per instruction at the primary cache is 5%. How much faster will
: the machine be if we add a second cache that has a 20ns access time for
: either a bit or a miss and is large enough to reduce the miss rate to
: main memory to 2%.
500MHZ => 2ns and main memory access time => 100 clock cycle
miss rate 5%
在单层的情况下
CPUtime=0.95*(1)+0.05*(1+100)=6clock cycle
但在双层纯牛肉的口感下
CPUtime=0.95*(1)+0.03*(1+10)+0.02*(1+10+100)
=0.95+0.33+2.22=3.5
最後 除去吧 就将...
=======
我倒是对 32bits physical address & 4-set 这种问题感到厌恶...
可以有神人写个供略嘛 >___<""
--
我绝对不会说 这是我的无名.........
http://www.wretch.cc/blog/chris750630
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 61.59.129.226
1F：推 gn00618777:嗯 一看就懂 谢谢 01/18 22:18
2F：推 lovefo:真厉害...我计组这麽烂 都懂了XD 01/18 22:58