(97交大电子)的题目 Consider the following MIPS code fragment: LD R1,45(R2) DADD R7,R1,R5 DSUB R8,R1,R6 OR R9,R5,R1 BNEZ R7,target DADD R10,R8,R5 XOR R2,R3,R4 (b) for the classical 5-stage MIPS processor,assume a register file that write in the first half of clock cycle and reads in the second half cycle forwarding . which of the dependences that you found become hazard and which do not? why? 解答为 from the pipeline above,we can find only 1&2,1&3 occur data hazard. other data dependences are solve by half-write half-read register file and "forwarding strategy".Hence,2 stalls may needed for instruction 2, and as a sequence,no more stall need for instruction 3. 我想问的是 1. 根据题目的题意 是有支援forwarding吗? 若有的话 1&3 并不会有data hazard的存在吧 (因为LD指令在执行完mem stage时，可将资料forwarding给DSUB的ALU作输入用 ，故DSUB没有hazard存在) 2. 若没有支援forwarding，1&2,1&3 occur data hazard是没错的。 那为何解答中写solve by half-write half-read register file and ""forwarding strategy""... 另一个想法是，要解决1&2,1&3的data hazard是需要将 DADD的ID stage跟DSUB 的IF stage各stall一个clock，外加forwarding才可解决。但题目没说清楚? 还是根本就是我没想清楚... 麻烦各位高手指导一下 谢谢!! --

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