97年的中山数位电路 Problem3 Design a circuit that implements the negative-edge-triggered D flip-flop with Clear and Preset using the basic gates such as NOT,AND,OR, NAND, and NOR. Problem5 Design a four-bit carry-lookahead adder using the basic gates such as NOT, AND,OR,NAND,NOR and XOR.(10%) By the four-bit carry-lookahead adder module (named CLA4), design a 16-bit carry-lookahead adder(5%).Let the basic gates take the same delay time as 1d. Determine the delay time of the critical path of the 16-bit carry-lookahead adder(5%). Problem6 (a)Write the code for a negative-edge-triggered D filp-fiop with synchronous reset in VHDL or Verilog HDL. (b)In VHDL or Verilog HDL, write the code for the traffic light controller, whose lighting sequences are as Figure P6. After the red lamp lights 3 cycles, the green lamp light 2 cycles. After the green lamp lights,the yellow lamp lights1 cycle. 拜托各位大大 因为小弟实在不太会这数位电路 所以烦请各位大大 赐给小弟解答 感激万分 -- 淡游 淡如云烟~~游在四方 --

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