http://board.byuu.org/viewtopic.php?f=3&t=1741 Back from vacation. We were successful in emulating the Cx4 using LLE during my vacation. We finished on June 15th. And now that I'm back, I've rewritten the code and merged it into bsnes official. With that, the very last HLE emulation code in bsnes has now been purged. I still have some more plans for bsnes v080, so I'm not going to bump the version number just yet. Plus I would like it if we could thoroughly test the new Cx4 LLE support to ensure it is bug-free. To that aim, if you have some time and would like to help test: please download bsnes v079.04 and cx4.bin. Place cx4.bin in the same folder as "Mega Man X 2 (U).sfc" and "Mega Man X 3 (U).sfc", and then do your best to play through the entire games with no cheat codes, and uncover all of the secrets that you can. If you find any bugs, or if the console window prints "invalid opcode" at any time, please send me a note on my forums. Thanks in advance to anyone who can help test this. http://bsnes.googlecode.com/files/bsnes_v079r04.tar.bz2 http://byuu.org/snes/cx4/cx4.bin ----- The emulation is as minimal as possible. If I don't see an opcode or feature actually used, I don't implement it. The one exception being that I do support the vector override functionality. And there are also dummy handlers for ld ?,$2e + loop, so that the chip won't stall out. But things like "byte 4" on rdram/wrram, the two-bit destination selections for all but ld, etc are treated as invalid opcodes, since we aren't 100% sure if they are there and work as we hypothesize. I also only map in known registers into the 256-entry register list. This leaves 90% of the map empty. The chip runs at 20MHz, and it will disable the ROM while running. DMA does transfer one byte at a time against the clock and also locks out the ROM. rdbus won't fetch from IRAM, only from ROM. DMA transfer only reads from ROM, and only writes to RAM. Unless someone verifies that they can do more, I'll leave it that way. I don't yet actually buffer the program ROM into the internal program RAM just yet, but that is on the to-do list. We aren't entirely sure how that works either, but my plan is to just lock the Cx4 CPU and load in 512-bytes. There's still a few unknown registers in $7f40-5f that I don't do anything with yet. The secondary chip disable is going to be the weirdest one, since MMX3 only has one chip. I'd really rather not have to specify the ROM mapping as two separate chips on MMX2 and as one on MMX3 just to support this, so I don't know yet. Save state support is of course there already. Speed hit is 118fps HLE -> 109fps LLE in most scenes. Not bad, honestly. --

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