作者ghost008 (0080)
看板Electronics
标题[问题]请教有关这个 Verilog 除频器的问题
时间Thu Aug 30 23:23:34 2018
小弟最近需要做一个FPGA的i2c master
不过因为之前没有接触过
所以看了几本书之後，又照着网路的几个范例兜出架构
但是跑 semilution时一直没办法让除频过的SCL送出波型
Trigger的条件明明都有达成，该拉的状态也都确认过了
卡了两天左右实在抓不到方向
硬着头皮上来问各位大神，希望能帮忙解惑哪个地方有问题
================Verilog Module
`timescale 1ns / 1ns
module SRAM_I2C(
clk_10us,reset,SDA,SCL,
bit_state,
write_down,
read_data,read_down,
Mux_EN1,Mux_EN2,Mux_EN3,Mux_EN4);
input clk_10us,reset;
inout SDA;
output reg SCL;
output reg Mux_EN1,Mux_EN2,Mux_EN3,Mux_EN4;
output reg [7:0]bit_state;
output reg write_down,read_down;
output reg [7:0]read_data;
reg isOut,tx_SDA;
reg [1:0]cnt;
reg [4:0]byte_state;
reg [7:0]write_data;
//for address use
parameter
write_address =8'b0000_0000,
write_chipaddress =8'b0000_0000,
write_bit =8'b0000_0000;
assign SDA = isOut ? tx_SDA : 1'bz;
//CLK Div for 10us
always @(posedge clk_10us or negedge reset)
begin
if(!reset)
cnt <=0;
else begin
if(cnt ==3)
cnt <=0;
else
cnt <= cnt +1'b1;
end
end
always @(posedge clk_10us or negedge reset)
begin
if(!reset)begin
tx_SDA <=0;
SCL <=0;
isOut <=0;
bit_state <=0;
byte_state <=0; //Check bytes
write_data <=0;
write_down <=1;
read_down <=0;
read_data <=0;
buf_time<=0;
Mux_EN1<=0;
Mux_EN2<=0;
Mux_EN3<=0;
Mux_EN4<=0;
end
else if(write_down==1 && read_down==0)begin//read enable
case(bit_state)
0:begin//start
if(cnt==0)begin SCL<=1;tx_SDA<=1;isOut <=1;end
if(cnt==1)begin SCL<=1;tx_SDA<=1;end
if(cnt==2)begin SCL<=1;tx_SDA<=0;end
if(cnt==3)begin SCL<=0;tx_SDA<=0;bit_state<=bit_state +1;
if(byte_state==3)write_data<=8'b10100001;else
write_data<=write_address;end
end
default:begin isOut <=0;end
endcase
end
end
endmodule
================Test Bench
`timescale 100ns / 100ns
module SRAM_I2C_TB;
// Inputs
reg clk_10us;
reg reset;
// Outputs
wire SCL;
wire [7:0] bit_state;
wire [7:0] read_data;
wire Mux_EN1;
wire Mux_EN2;
wire Mux_EN3;
wire Mux_EN4;
wire SDA;
SRAM_I2C uut (
.clk_10us(clk_10us),
.reset(reset),
.SDA(SDA),
.SCL(SCL),
.bit_state(bit_state),
.write_down(write_down),
.read_data(read_data),
.read_down(read_down),
.Mux_EN1(Mux_EN1),
.Mux_EN2(Mux_EN2),
.Mux_EN3(Mux_EN3),
.Mux_EN4(Mux_EN4)
);
//Generate CLK
reg [7:0] bit_states;
always begin
#50 clk_10us=!clk_10us;
end
initial begin
// Initialize Inputs
#0;
clk_10us = 0;
reset = 1;
#30;
reset = 0;
#5000 $finish;
end
endmodule
--
※ 发信站: 批踢踢实业坊(ptt.cc), 来自: 123.110.178.209
※ 文章网址: https://webptt.com/cn.aspx?n=bbs/Electronics/M.1535642616.A.CE6.html
※ 编辑: ghost008 (123.110.178.209), 08/30/2018 23:24:02
1F：→ TripleC: 你确定你要一直reset吗... 08/31 12:26
歹势 我知道可能效率很差或是写得很外行
不过我希望第一步的Waveform要能正确输出，再慢慢修改
※ 编辑: ghost008 (118.166.219.36), 08/31/2018 12:33:20
2F：→ TripleC: 你没抓到我说的重点 你的电路reset是active low 08/31 12:42
3F：→ TripleC: 你 testbench 这样写电路会一直在reset state 08/31 12:43
原来是initial的SCL=0 是Activie low，这样转态会读不到
现在可以动了 非常感谢!!!
※ 编辑: ghost008 (118.166.219.36), 08/31/2018 13:17:24