作者zzss2003 (brotherD)
看板Electronics
标题[请益] Open collector and Tri-Stating Outputs
时间Mon Aug 7 11:55:18 2017
各位好,小弟目前在自修"An Embedded Software Primer"。其中里面有一些看不懂的疑
问
图片:
http://imgur.com/a/97LLF
http://imgur.com/a/9cuOz
http://imgur.com/a/xWo9r
在第一张图片中,the open collector outputs, allows you to attach the outputs of
several devices together to drive a single signal. Unlike the usual outputs,
which drive signals high or drive them low, the open collector outputs can
drive their outputs low or let them float.
想请问一下这一段。open collector outputs可以让Chip 1跟Chip 2的outputs为low 或
float。是因为在Chip1跟Chip2的输出有一个inverter吗? 什麽是usual outputs?是指输出
没接其他的外部电路吗?
在第二张图片中,If several open collector outputs are attached to the same
signal, then the signal goes low if any of the outputs is driving low.
open collector outputs不是只有一个吗?为什麽会有好几个? 这里的same signal是指哪
个signal? pullup resistor上的signal吗?
同样在第二张图片中,为什麽一定要有pullup resistor?为什麽没有的话,INT/会float?
pullup resistor是接到VCC,就算没有这颗电阻,INT/也是high吧?
其中,Note also that you cannot omit the resistor and connect the INT/ signal
directly to VCC. If you did this, then you would have a bus fight on your hands
as soon as one of the devices tried to drive INT/ low, since the parts that
provide electrical power to your circuit would then try to keep INT/ high.
这句的意思是说,如果Chip 1或Chip 2想要给INT/ low,但VCC同时给high会导致bus
fight,但是,为什麽加上pullup resistor就不会发生呢?
谢谢前辈们看完这冗长又基本的问题,谢谢。
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1F:推 yudofu: 你先了解什麽是open collector跟floating 08/07 16:49
2F:→ mmonkeyboyy: 就是有 collector的输出 08/07 16:49
3F:→ mmonkeyboyy: wiki就有了 08/07 16:50
4F:→ Archer55b6: 我用CMOS跟你解释好了 08/19 18:39
5F:→ Archer55b6: 你先找个CMOS Inverter电路 08/19 18:39
6F:→ Archer55b6: usual output就是用MOS 08/19 18:39
7F:→ Archer55b6: 输出LOW时把输出端往下拉 08/19 18:39
8F:→ Archer55b6: 输出HIGH时把输出端往上拉 08/19 18:39
9F:→ Archer55b6: (跟VDD导通或GND导通) 08/19 18:39
10F:→ Archer55b6: 而open collector(CMOS是open drain) 08/19 18:39
11F:→ Archer55b6: 则是输出LOW时靶输出端往下拉 08/19 18:39
12F:→ Archer55b6: 输出HIGH时什麽都不拉 08/19 18:39
13F:→ Archer55b6: 所以若没接提昇电阻,输出端就会是开路的状态 08/19 18:39
14F:→ Archer55b6: 这麽做的好处就是两个O.D.输出可以接一起而不会造成短 08/19 18:39
15F:→ Archer55b6: 路(一个HI一个LO时 08/19 18:39
16F:→ Archer55b6: 形成一个AND闸的概念,只要其中一个输出LOW则输出LOW 08/19 18:40
17F:→ Archer55b6: ,全部都输出HIGH时才经由提升电阻接到正(MOS开路) 08/19 18:40