作者chun0416 (牛先生)
看板Electronics
标题[问题] FPGA 记忆体4port改8port
时间Wed Aug 5 15:35:54 2015
因为需求，我将原本Terasic所提供source code(记忆体存取为4port)改为8port
我是拉摄影机的影像资料给记忆体
改成8port後，单纯使用RD1RD2WR1WR2 或 RD3RD4WR3WR4都不会有问题
但是一次使用8个PORT後影像会跑掉
Sdram_Control u7 ( // HOST Side
.RESET_N(KEY[0]),
.CLK(sdram_ctrl_clk),
.WR1_DATA({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(800*600/2),
.WR1_LENGTH(8'h80),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(GPIO[0]),
// FIFO Write Side 2
.WR2_DATA({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
.WR2(sCCD_DVAL),
.WR2_ADDR(23'h100000),
.WR2_MAX_ADDR(23'h100000+800*600/2),
.WR2_LENGTH(8'h80),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(GPIO[0]),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(800*600/2),
.RD1_LENGTH(8'h80),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(23'h100000),
.RD2_MAX_ADDR(23'h100000+800*600/2),
.RD2_LENGTH(8'h80),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(~VGA_CTRL_CLK),
// FIFO Write Side 3
.WR3_DATA({1'b0,sCCD_G_2[11:7],sCCD_B_2[11:2]}),
.WR3(sCCD_DVAL_2),
.WR3_ADDR(23'h200000),
.WR3_MAX_ADDR(23'h200000+800*600/2),
.WR3_LENGTH(8'h80),
.WR3_LOAD(!DLY_RST_0),
.WR3_CLK(HSMC_CLKIN_n[2]),
// FIFO Write Side 4
.WR4_DATA({1'b0,sCCD_G_2[6:2],sCCD_R_2[11:2]}),
.WR4(sCCD_DVAL_2),
.WR4_ADDR(23'h300000),
.WR4_MAX_ADDR(23'h300000+800*600/2),
.WR4_LENGTH(8'h80),
.WR4_LOAD(!DLY_RST_0),
.WR4_CLK(HSMC_CLKIN_n[2]),
// FIFO Read Side 3
.RD3_DATA(Read_DATA3),
.RD3(Read),
.RD3_ADDR(23'h200000),
.RD3_MAX_ADDR(23'h200000+800*600/2),
.RD3_LENGTH(8'h80),
.RD3_LOAD(!DLY_RST_0),
.RD3_CLK(~VGA_CTRL_CLK),
// FIFO Read Side 4
.RD4_DATA(Read_DATA4),
.RD4(Read),
.RD4_ADDR(23'h300000),
.RD4_MAX_ADDR(23'h300000+800*600/2),
.RD4_LENGTH(8'h80),
.RD4_LOAD(!DLY_RST_0),
.RD4_CLK(~VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM(DRAM_DQM));
上述的资料传给READ_DATA後再转为RGB给VGA
在副程式里我加了PORT脚位跟判断3.4的读取写入，
请问是否我遗漏了什麽？
是否是加了两个PORT後会影响CLOCK?而使读取存取速度改变?
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1F：→ DaveLu: DRAM总频宽是否足够? 08/08 16:31