作者a22326284 (chin)
看板Electronics
标题Re: [问题] BCD adder verilog
时间Mon Oct 27 03:55:59 2014
※ 引述《gw112 (gw112)》之铭言：
: 题目：
: http://i.imgur.com/6ysXlWl.png
: 程式：
: http://i.imgur.com/T94Gwde.png
: 请问一下为什麽我的前4bit都会错呢？後4bit正确
: 另外有办法使assign减少到4个吗？
: 感谢
哎呀 一条一条回好麻烦呀....
以大大的图来说，假设:
X[7:4]=E X[3:0]=F
Y[7:4]=E Y[3:0]=F
c_in=0
FA1: X[3:0]+Y[3:0]+c_in => s_tmp[3:0] , ac_tmp
=>F + F + 0 = E , 1
FA2: s_tmp[3:0]+correction[3:0] => sum[3:0] , ac_correct
=>E + 6 = 4 , 1
ac = ac_tmp OR ac_correct
= 1 OR 1 => 1
FA3: X[7:4]+Y[7:4]+ac => stmp[7:4] , c_tmp
=>E + E + 1 = D , 1
FA4:s_tmp[7:4]+correction[7:4] => sum[7:4] , c_correct
=>D + 6 = 3 , 1
c_out = c_tmp OR c_correct
= 1 OR 1 => 1
大致上应该是这样 ~~
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