作者Uruzu (...)
看板Electronics
标题Re: [问题] veriog撰写问题
时间Thu Aug 6 00:19:33 2009
沿用之前的code
补个rising pulse
是否是你要的?
module add_sub(clk,reset,mod_n,incr,decr);
input clk,incr,decr,reset;
output [12:0] mod_n;
reg [12:0] mod_n;
reg incr_d, incr_2d;
reg decr_d, decr_2d;
wire incr_r = incr_d & ~incr_2d;
wire decr_r = decr_d & ~decr_2d;
always@(posedge clk)
begin
if(reset)
mod_n <= 13'd2000;
else
mod_n <= incr_r ? mod_n-13'd10 :
decr_r ? mod_n+13'd10 : mod_n;
end
always@(posedge clk)
begin
if(reset)
incr_d <= 1'b0;
incr_2d <= 1'b0;
decr_d <= 1'b0;
decr_2d <= 1'b0;
else begin
incr_d <= incr;
incr_2d <= incr_d;
decr_d <= decr;
decr_2d <= decr_d;
end
end
endmodule
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 118.169.81.57
1F：推 arclitetank:我猜应该就是这样~ 08/06 00:23
2F：推 felghana:这样会不会有race的问题阿 因为incr_r变high时 是在clk 08/06 00:38
3F：→ felghana:正缘触发 那到底是上面的always先做还是下面呢? 08/06 00:39
4F：→ felghana:要下面的先把incr_r先变high才会对 08/06 00:39