module add_sub(clk,reset,mod_n,incr,decr); input clk,incr,decr,reset; output[12:0] mod_n; reg [1:0] state,next_state; reg [12:0] mod_n; parameter s0=2'd0,s1=2'd1,s2=2'd2,s3=2'd3; always@(posedge clk) begin if(reset) state=s0; else state=next_state; end //s0:重置用 s1:增加mod_n s2:减少mod_n s3:维持mod_n always@(state) begin case(state) s0:mod_n=13'd2000; s1:mod_n=mod_n+13'd10; s2:mod_n=mod_n-13'd10; default:; endcase end //当incr变为high时增加mod_n //当decr变为high时减少mod_n always@(state or incr or decr) begin case(state) s0: next_state=s3; s1: if(decr) next_state=s1; else next_state=s3; s2: if(incr) next_state=s2; else next_state=s3; s3: if(incr) next_state=s2; else if(decr) next_state=s1; else next_state=s3; default: next_state=s0; endcase end endmodule 上面是我写的verilog 程式码 目的是把mod_n传到除频器当除频参数 所以藉由控制mod_n可以决定除频後的频率 我目前的问题是 使用quartus II烧录至FPGA後 电路的动作完全错误 和我所撰写的完全不同 想问版上的高手 我的code是不是有容易被合成软体误解的地方 我已经改了很多次还是一样 麻烦好心的高手指点一下 谢谢 我把compile之後的warning讯息贴上来 Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Warning: Circuit may not operate. Detected 23 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. ※ 编辑: felghana 来自: 58.114.132.207 (08/06 10:45)