Consider amachine which supports the following two instruction schedules for R class and I class instructions. Assume that IF steps take 25 ns, MEM steps of instruction executions require 45 ns and the other steps require 20 ns. 0 1 2 3 4 R class IF ID EX WB I class IF ID EX MEM WB (a)For a single cycle of a fixed length implementation, what is the minimum clcok cycle time? How long on average does it take to execute 100 instructions in neroseconds ? (b)For a single cycle of a variable length implementation, what is the minimum clcok cycle time? How long on average does it take to execute 100 instructions in neroseconds ? (c)For a multi-cycle implementation, what is the minimum clcok cycle time? How long on average does it take to execute 100 instructions in ns ? (d)For a 5 stage fully pipelined implementation, assuming there are no harzards, what is the minimum clcok cycle time? How long on average does it take to execute 100 instructions in neroseconds ? (e)Suppose we now have 6 stage pipelining by splitting a MEM stage into two parts:MEM1 and MEM2, and each takes 25 ns. Then assuming there are no harzards, and assuming we use the minimum clcok cycle time, what would be the speedup of the new implementation over the origianl 5 stage pipelining? (a) 1. MAX[(25+20+20+20),(25+20+20+45+20)]=130 ns 2. 130*100=13000 ns (b) 1. MIN[(25+20+20+20),(25+20+20+45+20)]=85 ns 2. 85*100*0.6 + 130*100*0.4 = 10300 ns (c) 1. MAX[25,20,20,45,20]= 45 ns 2. 85*100*0.6 + 130*100*0.4 = 10300 ns (d) 1. MAX[25,20,20,45,20]= 45 ns 2. 5*45+(100-1)*45= 4680 ns (e) 1. minimum clcok cycle time =25 ns 2. 6*25+(100-1)*25 = 2625 3. speed up = 4680/2625 请问这样观念有错吗? 谢谢指教 --

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