作者jason543 (报告班长 哩供啥米消威)
看板Electronics
标题[问题] vhdl做一个暂存器
时间Mon Dec 15 21:56:36 2008
小弟现在想用VHDL做一个暂存器
大致的结构如下
INPUT -> G -> F -> E -> D -> C -> B -> A -> OUT
但一次要读 7 个暂存器的资料
假如我今天一列资料串是这样输入111001011100101110010.....
读出来的资料要为 DATAOUT是从A开始读起 大概如下
1s 1110010
2s 1100101
3s 1001011......依此类推
我的程式如下
entity register_pn is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
data_in : IN STD_LOGIC;
reg_data_out : OUT STD_LOGIC_VECTOR (6 downto 0)
);
end register_pn;
architecture Behavioral of register_pn is
begin
process (clk,reset)
variable reg_a,reg_b,reg_c,reg_d,reg_e,reg_f,reg_g : STD_LOGIC;
variable reg_a1 : STD_LOGIC;
begin
if (reset = '0') then
reg_a:='0';
reg_b:='0';
reg_c:='0';
reg_d:='0';
reg_e:='0';
reg_f:='0';
reg_g:='0';
reg_a1:='0';
reg_data_out <= "0000000";
elsif (reset = '1' and clk'event and clk = '0') then
reg_a:=reg_b;
reg_b:=reg_c;
reg_c:=reg_d;
reg_d:=reg_e;
reg_f:=reg_f;
reg_f:=reg_g;
reg_g:=reg_a1;
data_in<=reg_a1;
reg_data_out(0) <= reg_a;
reg_data_out(1) <= reg_b;
reg_data_out(2) <= reg_c;
reg_data_out(3) <= reg_d;
reg_data_out(4) <= reg_e;
reg_data_out(5) <= reg_f;
reg_data_out(6) <= reg_g;
end if;
end process;
end Behavioral;
现在遇到的困难是 出现一个ERROR
Object data_in of mode IN can not be updated
应该是说 IN 这边没办法丢新的资料进来
不太懂说为什麽无法丢 我只是把下一个资料丢到G而已 然後做移位
请版上的高手们帮帮忙吧 谢谢... 感恩
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 140.126.131.61