作者peliuya (伪美少女学园长)
看板Electronics
标题Re: [问题] verilog 建立 table 问题
时间Tue Dec 9 16:24:10 2008
※ 引述《sasako (只想把你留在心中)》之铭言：
: ※ 引述《peliuya (伪美少女学园长)》之铭言：
: : 我想用 verilog 建立一个 sin 的表格，其为200个14bit的阵列
: : 想使其成为 parameter ，不知道该如何撰写其语法。
: : 还是说 无法用 parameter 宣告？
: : 只能宣告为 reg ，再搭配 initial 指定？
: : 如果是後者的话， 语法该怎麽描述？
: : 感谢各位先进。
: 200个是指可以输入200种角度吗？
: 然後每个值量化後的bit数是14bit？
: 你想存成flip flop的形式（sequential）
: 还是assign给值的方式（combinational）
我用VHDL撰写的语法为
type sin_data is array(0 to 199) of integer;
signal sin_table:sin_data:=
{ 0 ,1029 ,2058 ,3084 ,4107 ,5126 ,6140 ,7148 ,8149 ,9142 ,
10126,11100,12063,13014,13952,14876,15786,16680,17558,18418,
19261,20084,20887,21670,22431,23170,23887,24580,25248,25892,
26510,27102,27667,28205,28715,29197,29649,30073,30467,30831,
31164,31467,31739,31979,32188,32365,32510,32623,32703,32752,
32767,32752,32703,32623,32510,32365,32188,31979,31739,31467,
31164,30831,30467,30073,29649,29197,28715,28205,27667,27102,
26510,25892,25248,24580,23887,23170,22431,21670,20887,20084,
19261,18418,17558,16680,15786,14876,13952,13014,12063,11100,
10126,9142 ,8149 ,7148 ,6140 ,5126 ,4107 ,3084 ,2058 ,1029,
0 ,-1029 ,-2058 ,-3084 ,-4107 ,-5126 ,-6140 ,-7148 ,-8149 ,-9142 ,
-10126,-11100,-12063,-13014,-13952,-14876,-15786,-16680,-17558,-18418,
-19261,-20084,-20887,-21670,-22431,-23170,-23887,-24580,-25248,-25892,
-26510,-27102,-27667,-28205,-28715,-29197,-29649,-30073,-30467,-30831,
-31164,-31467,-31739,-31979,-32188,-32365,-32510,-32623,-32703,-32752,
-32767,-32752,-32703,-32623,-32510,-32365,-32188,-31979,-31739,-31467,
-31164,-30831,-30467,-30073,-29649,-29197,-28715,-28205,-27667,-27102,
-26510,-25892,-25248,-24580,-23887,-23170,-22431,-21670,-20887,-20084,
-19261,-18418,-17558,-16680,-15786,-14876,-13952,-13014,-12063,-11100,
-10126,-9142 ,-8149 ,-7148 ,-6140 ,-5126 ,-4107 ,-3084 ,-2058 ,-1029
}
即数值於-32767~32767之间，今要改以verilog的方式来撰写
却不知道该如何让其宣告为参数的型态。
以方便我在接下来的程式中，取出某一向量值来做运算。
请各位帮帮忙 ^^
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1F：推 bighead319:你就是要造一个size为200个word的RAM，用case写就好了 12/09 22:59