作者tkhan (脑残绿吱吱)
看板Electronics
标题Re: [问题] verilog 组合逻辑的delay
时间Mon Oct 27 09:48:17 2008
※ 引述《pdgwu (熙)》之铭言：
: // module decoder
: input clk;
: input reset;
: input [7:0] inData;
: output [15:0] outData;
: reg [3:0] state;
: reg [3:0] next_state;
: // sequential logic
: always @(posedge clk or posedge reset)
: begin
: if(reset)
: state <= S0;
: else
: state <= next_state;
: end
: // combinational logic : FSM and Decoder
: always @(state or inData)
: begin
: outData = 16'h0000;
: case(state)
: S0:
: begin
: // ...
: next_state = S1;
: end
: S1:
: begin
: // ...
: case(inData[3:0])
: 4'b0000:
: outData = 16'h1234;
: 4'b0001:
: outData = 16'h5678;
: ...
: endcase
: next_state = S2;
: end
: S2:
: ...(略)
: default:
: ...
: endcase
: end
always @(state or inData)
begin
case(state)
S0:
begin
case(inData)
4'b0000: next_state = S1;
4'b0001: next_state = S2;
default: next_state = S3;
endcase
end
S1: next_state = S3;
S2: next_state = S3;
S3:
....(略)
default:
endcase
end
always @(posedge clk or negedge reset)
begin
if(!reset_)
outData <= 16'h0;
else
begin
case(next_state)
S0: outData <= 16'h0;
S1: outData <= 16'h1234;
S2: outData <= 16'h5678;
S3: ....(略)
default:
endcase
end
end
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