作者finalhaven (爆炸神威)
站内Electronics
标题[问题]verilog一问
时间Fri May 16 00:04:56 2008
module led_rat(clkin,reset,led);
input clkin;
input reset;
output [7:0]led;
reg [23:0]q;
reg [7:0]led;
reg div_clkout;
reg flag;
always@( posedge reset or negedge clkin)
begin
if(reset)
begin
div_clkout = 0;
q = 0;
end
else if (q == 50000000)
begin
div_clkout = ~div_clkout;
q = 0;
end
else
q=q+1;
end
always@(posedge reset or negedge div_clkout)
begin
if(reset)
begin
led = 0;
flag = 0;
end
else if (flag == 0)
begin
led = led << 1;
flag = 1;
end
else if (flag == 1)
begin
led = led >> 1;
flag = 0;
end
else
led = led;
end
endmodule
这个程式的功能是要做除频＋LED移位
可是合成完之後，会说找不到CLK....
就是clkin那个脚位，没有clk
有大大可以帮我看一下吗?谢谢
以下是合成完的timing report
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay: 9.317ns (Levels of Logic = 4)
Source: reset (PAD)
Destination: led<3> (PAD)
Data Path: reset to led<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 reset_IBUF (reset_IBUF)
LUT2:I0->O 2 0.479 0.915 _n00001 (flag)
LUT3:I1->O 4 0.479 0.779 led<1>1 (led_1_OBUF)
OBUF:I->O 4.909 led_3_OBUF (led<3>)
----------------------------------------
Total 9.317ns (6.582ns logic, 2.735ns route)
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design 找不到clock...
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.317ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay: 9.317ns (Levels of Logic = 4)
Source: reset (PAD)
Destination: led<3> (PAD)
Data Path: reset to led<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 reset_IBUF (reset_IBUF)
LUT2:I0->O 2 0.479 0.915 _n00001 (flag)
LUT3:I1->O 4 0.479 0.779 led<1>1 (led_1_OBUF)
OBUF:I->O 4.909 led_3_OBUF (led<3>)
----------------------------------------
Total 9.317ns (6.582ns logic, 2.735ns route)
(70.6% logic, 29.4% route)
=========================================================================
--
当在跑向终点的漫长旅程上，请不要忘记最初起点的梦想!
--
※ 发信站: 批踢踢实业坊(ptt.cc)
◆ From: 220.133.46.8
1F：推 DinoZavolta:不好意思，在你的code中，我也找不到"CLK"这讯号~ @@" 05/16 00:09
2F：→ DinoZavolta:如果方便的话，可否连合成的script也一并贴上来~ 05/16 00:11
※ 编辑: finalhaven 来自: 220.133.46.8 (05/16 00:13)
3F：推 DinoZavolta:ㄜ... 抱歉，我以为你是用 Synopsys DC 去合的~ 05/16 00:28
4F：推 tkhan:先把blocking 和 non-blocking搞懂.. 05/16 01:01
5F：推 bighead319:先不管code的问题，光是缩排都没弄好有人就不想看了 05/16 01:12
6F：→ sasako:很难看懂...ㄏㄏ 只有个小问题 为什麽clk是负缘触发??? 05/16 02:17
7F：→ sasako:我是觉得先把好的coding style建立起来很重要.. 05/16 02:18
8F：→ sasako:不然你debug很麻烦 05/16 02:18
9F：→ sasako:以後你想再trace自己的code 大概也是看不懂= =" 05/16 02:19