作者you2 (So do I)
看板Electronics
标题Re: [问题] OPA模拟,闭回路看phase margin,对吗?
时间Sat Nov 24 00:36:22 2007
※ 引述《windyddd (ddd)》之铭言:
: ※ 引述《coa481 (手机快复活-_-||)》之铭言:
: : 请教各位前辈:
: : 在模拟OPA时,单就该OPA的特性做模拟时,如:
: : 开回路增益、Phase Margin等,所得到的值
: : 与接成闭回路(假设直接由输出接回输入)所得到值,哪一个才是对的阿??
: : 我试的结果,当我用开回路模拟的话,Gain很小,很多MOS都在Liner,甚至有off的
: : 而接成闭回路後,不但Gain上升,PM也稳定约70度
: : 正常而言,应该是失败吧~可是又会被闭回路所看到的结果给迷惑了...
: : 特别是有一位业界的朋友,说他们都直接模拟闭回路,这样我更迷惑了...
: : 另外,以一个简单的two-stage OPA来讲,假设输入对用PMOS
: : 那这2颗的body,可以直接接它们的source吗?
: : (正常不是都要接到最正的电压?)
: : 请帮我解惑~谢谢。
: I recommend you read Jacob Baker's book on Operational Amp. I
: He clearly depicts every detail on testing open loop gain,
: freq. response, compensation..so on so forth.
: Good Luck
Why do we need to know the phase margin?
The system is unstable because it is a closed-loop system.
That's why I said that it doesn't make sense to talk about the phase margin
when the system is an open-loop system.
We are suppposed to measure the phase margin of the closed-loop system using
the bode plot of the loop gain rather than the open-loop gain or the closed-loop
gain. When the feedback factor, beta, is equal to unity, it's a so-called worst
case. Under this condition, the loop gain is equivalent to the open-loop gain.
That's why somebody measures the phase margin of the closed-loop system based on
the open-loop gain. They want to know the phase margin for the worst case.
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