SATA spec.-SSC jitter measurement (CDR corner frequency) In SATA specification, jitter is defined as the difference in time between a data transition and the associated Reference Clock event for Gen1x, Gen2i and Gen2x. SATA assumes a BER target of less than 10-12. The Reference Clock is extracted from a serial data stream using either a PLL (hardware) or a clock recovery algorithm (software). Reference Clock PLL are defined as type 2 PLL with a -3 dB corner frequency fc3db = fBAUD / N. Several corner frequencies are provided in the jitter budget fc3db = fBAUD / 10 (Gen2i, Gen2m), fc3db = fBAUD / 500 (Gen2i, Gen2m), fc3db = fBAUD / 1667 (Gen1x, Gen2x).For Gen2i and Gen2m, transmitters and receivers shall meet fBAUD / 10 and fBAUD / 500 specifications. How to calculate the technical origin of the number 1667 or 500? Is there some mathematical or technical explanation for it? I have read the Annex C in MJSQ (Method for Jitter and Signal Quality) document, but I can't get the answer . Thank you!! 因为之前在国外的论坛发问 但没得到答案 所以就直接复制过来用烂英文PO版问了 想问 fc3db = fBAUD / 500的 1/500或 1/1667 这数字怎麽来的？ 只知道是依 jitter budget 推出来的 但比较详细的数学就不知道怎麽导 不知道有没有人清楚 谢谢！ --

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