作者magician1 (不如歸去)
看板Electronics
標題[問題] Verilog
時間Sat Mar 20 01:52:59 2010
sub_25b(a, b, c);
input [24:0] a;
input [24:0] b;
output [24:0] c;
assign c = a - b;
endmodule
module CIC_FILTER(v_in, v_out, clk, clk1, reset);
input [15:0] v_in;
output reg [15:0] v_out;
reg [24:0] x_tap[5:0];
reg [24:0] y_tap[2:0];
reg [24:0] tmp;
reg [24:0] tmp_1;
wire [24:0] tmp_out;
reg [24:0] tmp_2;
reg [24:0] tmp_3;
wire [24:0] tmp_out1;
reg [1:0] state;
reg [1:0] state_1;
reg [24:0] x_tmp_2;
wire [24:0] x_in;
sub_25b s0(.a(tmp), .b(tmp_1), .c(tmp_out));
assign x_in = {{9{v_in[15]}}, v_in[15:0]};
always @(negedge clk or negedge reset) begin
if(!reset) begin
state[1:0] <= 2'b0;
end
else begin
state[1:0] <= state[1:0] + 1;
end
end
always @(negedge clk1 or negedge reset) begin
if(!reset) begin
state_1[1:0] <= 2'b0;
end
else begin
state_1[1:0] <= state_1[1:0] + 1;
end
end
always @(negedge clk or negedge reset) begin
if(!reset) begin
x_tap[0] <= 0;
x_tap[1] <= 0;
x_tap[2] <= 0;
x_tap[3] <= 0;
x_tap[4] <= 0;
x_tap[5] <= 0;
tmp <= 0;
tmp_1 <= 0;
end
else begin
case(state[1:0])
2'b00: begin
tmp <= x_in;
tmp_1 <= x_tap[1];
end
2'b01: begin
tmp <= tmp_out;
tmp_1 <= x_tap[3];
x_tap[2] <= tmp_out;
x_tap[3] <= x_tap[2];
end
2'b10: begin
tmp <= tmp_out;
tmp_1 <= x_tap[5];
x_tap[4] <= tmp_out;
x_tap[5] <= x_tap[4];
end
2'b11: begin
x_tmp_2 <= tmp_out;
x_tap[0] <= x_in;
x_tap[1] <= x_tap[0];
end
endcase
end
end
endmodule
請問 這些寫法 有哪裡不妥嗎 謝謝
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◆ From: 115.43.49.101
※ 編輯: magician1 來自: 115.43.49.101 (03/20 01:53)
※ 編輯: magician1 來自: 115.43.49.101 (03/20 01:55)
1F：噓 horsehead:噓你 03/20 13:21
2F：→ cnprince:問題沒頭沒尾的，你想人家回答你什麼 = = 03/20 14:50
3F：噓 luckyBF:有人開炮~!!小弟補刀~~XD 03/20 15:12